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<h1>Synchronous Serial Controller Interface Peripheral</h1>
<null><a name="SSC"></a><b>SSC</b> <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_SSC">AT91S_SSC</a>)</font></i><b>  0xFFFD4000 </b><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_BASE_SSC">AT91C_BASE_SSC</a>)</font></i>
<table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1">Periph ID <a href="#AIC">AIC</a></font></th><th bgcolor="#FFFFCC"><font size="-1">Symbol</font></th><th bgcolor="#FFFFCC"><font size="-1">Description</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>8</b> </font></td><td><font size="-1"><i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91C_ID_SSC">AT91C_ID_SSC</a>)</font></i></font></td><td><font size="-1">Serial Synchronous Controller</font></td></tr>
</null></table><br><table border=1 cellpadding=3 cellspacing=0><null><th bgcolor="#FFFFCC"><font size="-1"><b>Signal</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Symbol</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>PIO controller</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b>
</font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b>TD</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA17_TD      ">AT91C_PA17_TD      </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 17</font></td><td><font size="-1">SSC Transmit data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>TF</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA15_TF      ">AT91C_PA15_TF      </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 15</font></td><td><font size="-1">SSC Transmit Frame Sync</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>RK</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA19_RK      ">AT91C_PA19_RK      </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 19</font></td><td><font size="-1">SSC Receive Clock</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>RD</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA18_RD      ">AT91C_PA18_RD      </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 18</font></td><td><font size="-1">SSC Receive Data</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>RF</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA20_RF      ">AT91C_PA20_RF      </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 20</font></td><td><font size="-1">SSC Receive Frame Sync</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b>TK</b></font></td><td><font size="-1"><i><font size="-1">(<a href="#AT91C_PA16_TK      ">AT91C_PA16_TK      </a>)</font></i></font></td><td><font size="-1"><a href="#PIOA">PIOA</a>  Periph: A Bit: 16</font></td><td><font size="-1">SSC Transmit Clock</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_CfgPIO">AT91F_SSC_CfgPIO</a></b></font></td><td><font size="-1">Configure PIO controllers to drive SSC signals</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_CfgPMC">AT91F_SSC_CfgPMC</a></b></font></td><td><font size="-1">Enable Peripheral clock in PMC for SSC</font></td></tr>
</null></table><br><br></null><a name="SSC"></a><h2>SSC Software API <i><font size="-1">(<a href="AT91SAM7S256_h.html#AT91S_SSC">AT91S_SSC</a>)</font></i></h2>
<a name="SSC"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_CR">SSC_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_CMR">SSC_CMR</a></font></td><td><font size="-1">Clock Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_RCMR">SSC_RCMR</a></font></td><td><font size="-1">Receive Clock ModeRegister</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_RFMR">SSC_RFMR</a></font></td><td><font size="-1">Receive Frame Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x18</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_TCMR">SSC_TCMR</a></font></td><td><font size="-1">Transmit Clock Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x1C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_TFMR">SSC_TFMR</a></font></td><td><font size="-1">Transmit Frame Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x20</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_RHR">SSC_RHR</a></font></td><td><font size="-1">Receive Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x24</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_THR">SSC_THR</a></font></td><td><font size="-1">Transmit Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x30</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_RSHR">SSC_RSHR</a></font></td><td><font size="-1">Receive Sync Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x34</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_TSHR">SSC_TSHR</a></font></td><td><font size="-1">Transmit Sync Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x40</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_SR">SSC_SR</a></font></td><td><font size="-1">Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x44</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_IER">SSC_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x48</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_IDR">SSC_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4C</b></font></td><td><font size="-1"><a href="AT91SAM7S256_SSC.html#SSC_IMR">SSC_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1">SSC_RPR (<a href="AT91SAM7S256_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x104</b></font></td><td><font size="-1">SSC_RCR (<a href="AT91SAM7S256_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x108</b></font></td><td><font size="-1">SSC_TPR (<a href="AT91SAM7S256_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10C</b></font></td><td><font size="-1">SSC_TCR (<a href="AT91SAM7S256_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x110</b></font></td><td><font size="-1">SSC_RNPR (<a href="AT91SAM7S256_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x114</b></font></td><td><font size="-1">SSC_RNCR (<a href="AT91SAM7S256_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x118</b></font></td><td><font size="-1">SSC_TNPR (<a href="AT91SAM7S256_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x11C</b></font></td><td><font size="-1">SSC_TNCR (<a href="AT91SAM7S256_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x120</b></font></td><td><font size="-1">SSC_PTCR (<a href="AT91SAM7S256_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x124</b></font></td><td><font size="-1">SSC_PTSR (<a href="AT91SAM7S256_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_Configure">AT91F_SSC_Configure</a></b></font></td><td><font size="-1">Configure SSC</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_DisableRx">AT91F_SSC_DisableRx</a></b></font></td><td><font size="-1">Disable receiving datas</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_SendFrame">AT91F_SSC_SendFrame</a></b></font></td><td><font size="-1">Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_DisableIt">AT91F_SSC_DisableIt</a></b></font></td><td><font size="-1">Disable SSC IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_EnableRx">AT91F_SSC_EnableRx</a></b></font></td><td><font size="-1">Enable receiving datas</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_ReceiveFrame">AT91F_SSC_ReceiveFrame</a></b></font></td><td><font size="-1">Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_EnableIt">AT91F_SSC_EnableIt</a></b></font></td><td><font size="-1">Enable SSC IT</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_SetBaudrate">AT91F_SSC_SetBaudrate</a></b></font></td><td><font size="-1">Set the baudrate according to the CPU clock</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_IsInterruptMasked">AT91F_SSC_IsInterruptMasked</a></b></font></td><td><font size="-1">Test if SSC Interrupt is Masked </font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_GetInterruptMaskStatus">AT91F_SSC_GetInterruptMaskStatus</a></b></font></td><td><font size="-1">Return SSC Interrupt Mask Status</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_DisableTx">AT91F_SSC_DisableTx</a></b></font></td><td><font size="-1">Disable sending datas</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM7S256_h.html#AT91F_SSC_EnableTx">AT91F_SSC_EnableTx</a></b></font></td><td><font size="-1">Enable sending datas</font></td></tr>
</null></table></null><h2>SSC Register Description</h2>
<null><a name="SSC_CR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_CR  <i>Control Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_CR">AT91C_SSC_CR</a></i> 0xFFFD4000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_RXEN"></a><b>SSC_RXEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXEN">AT91C_SSC_RXEN</a></font></td><td><b>Receive Enable</b><br>0: No effect.<br>1: Enables Receive if RXDIS is not set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_RXDIS"></a><b>SSC_RXDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXDIS">AT91C_SSC_RXDIS</a></font></td><td><b>Receive Disable</b><br>0: No effect.<br>1: Disables Receive.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="SSC_TXEN"></a><b>SSC_TXEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXEN">AT91C_SSC_TXEN</a></font></td><td><b>Transmit Enable</b><br>0: No effect.<br>1: Enables Transmit if TXDIS is not set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="SSC_TXDIS"></a><b>SSC_TXDIS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXDIS">AT91C_SSC_TXDIS</a></font></td><td><b>Transmit Disable</b><br>0: No effect.<br>1: Disables Transmit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15</td><td align="CENTER"><a name="SSC_SWRST"></a><b>SSC_SWRST</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_SWRST">AT91C_SSC_SWRST</a></font></td><td><b>Software Reset</b><br>0: No effect.<br>1: Performs a software reset. Has priority on any other bit in SSC_CR.</td></tr>
</null></table>
<a name="SSC_CMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_CMR  <i>Clock Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_CMR">AT91C_SSC_CMR</a></i> 0xFFFD4004</font></null></ul><br>Clock Divider<br>0: The Clock Divider is not active.<br>Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.<a name="SSC_RCMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_RCMR  <i>Receive Clock ModeRegister</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RCMR">AT91C_SSC_RCMR</a></i> 0xFFFD4010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="SSC_CKS"></a><b>SSC_CKS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS">AT91C_SSC_CKS</a></font></td><td><b>Receive/Transmit Clock Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_CKS_DIV"></a><b>SSC_CKS_DIV</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS_DIV">AT91C_SSC_CKS_DIV</a></font></td><td><br>Divided Clock</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_CKS_TK"></a><b>SSC_CKS_TK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS_TK">AT91C_SSC_CKS_TK</a></font></td><td><br>TK Clock signal</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKS_RK"></a><b>SSC_CKS_RK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS_RK">AT91C_SSC_CKS_RK</a></font></td><td><br>RK pin</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4..2</td><td align="CENTER"><a name="SSC_CKO"></a><b>SSC_CKO</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO">AT91C_SSC_CKO</a></font></td><td><b>Receive/Transmit Clock Output Mode Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_CKO_NONE"></a><b>SSC_CKO_NONE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO_NONE">AT91C_SSC_CKO_NONE</a></font></td><td><br>Receive/Transmit Clock Output Mode: None RK pin: Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_CKO_CONTINOUS"></a><b>SSC_CKO_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO_CONTINOUS">AT91C_SSC_CKO_CONTINOUS</a></font></td><td><br>Continuous Receive/Transmit Clock RK pin: Output</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKO_DATA_TX"></a><b>SSC_CKO_DATA_TX</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO_DATA_TX">AT91C_SSC_CKO_DATA_TX</a></font></td><td><br>Receive/Transmit Clock only during data transfers RK pin: Output</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_CKI"></a><b>SSC_CKI</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKI">AT91C_SSC_CKI</a></font></td><td><b>Receive/Transmit Clock Inversion</b><br>0: The data and the Frame Sync signal are sampled on Receive Clock falling edge.<br>1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge.<br>CKI affects only the Receive Clock and not the output clock signal.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_START"></a><b>SSC_START</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START">AT91C_SSC_START</a></font></td><td><b>Receive/Transmit Start Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_START_CONTINOUS"></a><b>SSC_START_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_CONTINOUS">AT91C_SSC_START_CONTINOUS</a></font></td><td><br>Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_START_TX"></a><b>SSC_START_TX</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_TX">AT91C_SSC_START_TX</a></font></td><td><br>Transmit/Receive start</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_START_LOW_RF"></a><b>SSC_START_LOW_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_LOW_RF">AT91C_SSC_START_LOW_RF</a></font></td><td><br>Detection of a low level on RF input</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_START_HIGH_RF"></a><b>SSC_START_HIGH_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_HIGH_RF">AT91C_SSC_START_HIGH_RF</a></font></td><td><br>Detection of a high level on RF input</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_START_FALL_RF"></a><b>SSC_START_FALL_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_FALL_RF">AT91C_SSC_START_FALL_RF</a></font></td><td><br>Detection of a falling edge on RF input</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_START_RISE_RF"></a><b>SSC_START_RISE_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_RISE_RF">AT91C_SSC_START_RISE_RF</a></font></td><td><br>Detection of a rising edge on RF input</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SSC_START_LEVEL_RF"></a><b>SSC_START_LEVEL_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_LEVEL_RF">AT91C_SSC_START_LEVEL_RF</a></font></td><td><br>Detection of any level change on RF input</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SSC_START_EDGE_RF"></a><b>SSC_START_EDGE_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_EDGE_RF">AT91C_SSC_START_EDGE_RF</a></font></td><td><br>Detection of any edge on RF input</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SSC_START_0"></a><b>SSC_START_0</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_0">AT91C_SSC_START_0</a></font></td><td><br>Compare 0</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">23..16</td><td align="CENTER"><a name="SSC_STTDLY"></a><b>SSC_STTDLY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_STTDLY">AT91C_SSC_STTDLY</a></font></td><td><b>Receive/Transmit Start Delay</b><br>If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception/transmission.<br>When the Receiver/Transmitter is programmed to start synchronously with the Transmitter/Receiver, the delay is also applied.<br>Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive/Transmit Sync Data) reception.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SSC_PERIOD"></a><b>SSC_PERIOD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_PERIOD">AT91C_SSC_PERIOD</a></font></td><td><b>Receive/Transmit Period Divider Selection</b><br>This field selects the divider to apply to the selected Receive/Transmit Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive/Transmit Clock.</td></tr>
</null></table>
<a name="SSC_RFMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_RFMR  <i>Receive Frame Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RFMR">AT91C_SSC_RFMR</a></i> 0xFFFD4014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">4..0</td><td align="CENTER"><a name="SSC_DATLEN"></a><b>SSC_DATLEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_DATLEN">AT91C_SSC_DATLEN</a></font></td><td><b>Data Length</b><br>The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver/Transmitter. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_LOOP"></a><b>SSC_LOOP</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_LOOP">AT91C_SSC_LOOP</a></font></td><td><b>Loop Mode</b><br>0: Normal operating mode.<br>1: RD is driven by TD, RF is driven by TF and TK drives RK.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_MSBF"></a><b>SSC_MSBF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_MSBF">AT91C_SSC_MSBF</a></font></td><td><b>Most Significant Bit First</b><br>0: The lowest significant bit of the data register is sampled first in the bit stream.<br>1: The most significant bit of the data register is sampled first in the bit stream.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_DATNB"></a><b>SSC_DATNB</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_DATNB">AT91C_SSC_DATNB</a></font></td><td><b>Data Number per Frame</b><br>This field defines the number of data words to be received/transfered after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SSC_FSLEN"></a><b>SSC_FSLEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSLEN">AT91C_SSC_FSLEN</a></font></td><td><b>Receive/Transmit Frame Sync length</b><br>Receive:<br>This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. If 0, the Receive Frame Sync Sig-nal is generated during one Receive Clock period and up to a 16-clock period pulse length is possible.<br>Transmit:<br>This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..20</td><td align="CENTER"><a name="SSC_FSOS"></a><b>SSC_FSOS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS">AT91C_SSC_FSOS</a></font></td><td><b>Receive/Transmit Frame Sync Output Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_FSOS_NONE"></a><b>SSC_FSOS_NONE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_NONE">AT91C_SSC_FSOS_NONE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_FSOS_NEGATIVE"></a><b>SSC_FSOS_NEGATIVE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_NEGATIVE">AT91C_SSC_FSOS_NEGATIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Negative Pulse</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_FSOS_POSITIVE"></a><b>SSC_FSOS_POSITIVE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_POSITIVE">AT91C_SSC_FSOS_POSITIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Positive Pulse</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_FSOS_LOW"></a><b>SSC_FSOS_LOW</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_LOW">AT91C_SSC_FSOS_LOW</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_FSOS_HIGH"></a><b>SSC_FSOS_HIGH</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_HIGH">AT91C_SSC_FSOS_HIGH</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_FSOS_TOGGLE"></a><b>SSC_FSOS_TOGGLE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_TOGGLE">AT91C_SSC_FSOS_TOGGLE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SSC_FSEDGE"></a><b>SSC_FSEDGE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSEDGE">AT91C_SSC_FSEDGE</a></font></td><td><b>Frame Sync Edge Detection</b><br>Determines which edge on Frame Sync will generate the interrupt RXSYN/TXSYN in the SSC Status Register.<br>0: Positive Edge Detection<br>1: Negative Edge Detection</td></tr>
</null></table>
<a name="SSC_TCMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_TCMR  <i>Transmit Clock Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TCMR">AT91C_SSC_TCMR</a></i> 0xFFFD4018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="SSC_CKS"></a><b>SSC_CKS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS">AT91C_SSC_CKS</a></font></td><td><b>Receive/Transmit Clock Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_CKS_DIV"></a><b>SSC_CKS_DIV</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS_DIV">AT91C_SSC_CKS_DIV</a></font></td><td><br>Divided Clock</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_CKS_TK"></a><b>SSC_CKS_TK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS_TK">AT91C_SSC_CKS_TK</a></font></td><td><br>TK Clock signal</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKS_RK"></a><b>SSC_CKS_RK</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKS_RK">AT91C_SSC_CKS_RK</a></font></td><td><br>RK pin</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4..2</td><td align="CENTER"><a name="SSC_CKO"></a><b>SSC_CKO</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO">AT91C_SSC_CKO</a></font></td><td><b>Receive/Transmit Clock Output Mode Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_CKO_NONE"></a><b>SSC_CKO_NONE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO_NONE">AT91C_SSC_CKO_NONE</a></font></td><td><br>Receive/Transmit Clock Output Mode: None RK pin: Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_CKO_CONTINOUS"></a><b>SSC_CKO_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO_CONTINOUS">AT91C_SSC_CKO_CONTINOUS</a></font></td><td><br>Continuous Receive/Transmit Clock RK pin: Output</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_CKO_DATA_TX"></a><b>SSC_CKO_DATA_TX</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKO_DATA_TX">AT91C_SSC_CKO_DATA_TX</a></font></td><td><br>Receive/Transmit Clock only during data transfers RK pin: Output</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_CKI"></a><b>SSC_CKI</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_CKI">AT91C_SSC_CKI</a></font></td><td><b>Receive/Transmit Clock Inversion</b><br>0: The data and the Frame Sync signal are sampled on Receive Clock falling edge.<br>1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge.<br>CKI affects only the Receive Clock and not the output clock signal.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_START"></a><b>SSC_START</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START">AT91C_SSC_START</a></font></td><td><b>Receive/Transmit Start Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_START_CONTINOUS"></a><b>SSC_START_CONTINOUS</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_CONTINOUS">AT91C_SSC_START_CONTINOUS</a></font></td><td><br>Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_START_TX"></a><b>SSC_START_TX</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_TX">AT91C_SSC_START_TX</a></font></td><td><br>Transmit/Receive start</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_START_LOW_RF"></a><b>SSC_START_LOW_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_LOW_RF">AT91C_SSC_START_LOW_RF</a></font></td><td><br>Detection of a low level on RF input</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_START_HIGH_RF"></a><b>SSC_START_HIGH_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_HIGH_RF">AT91C_SSC_START_HIGH_RF</a></font></td><td><br>Detection of a high level on RF input</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_START_FALL_RF"></a><b>SSC_START_FALL_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_FALL_RF">AT91C_SSC_START_FALL_RF</a></font></td><td><br>Detection of a falling edge on RF input</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_START_RISE_RF"></a><b>SSC_START_RISE_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_RISE_RF">AT91C_SSC_START_RISE_RF</a></font></td><td><br>Detection of a rising edge on RF input</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SSC_START_LEVEL_RF"></a><b>SSC_START_LEVEL_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_LEVEL_RF">AT91C_SSC_START_LEVEL_RF</a></font></td><td><br>Detection of any level change on RF input</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SSC_START_EDGE_RF"></a><b>SSC_START_EDGE_RF</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_EDGE_RF">AT91C_SSC_START_EDGE_RF</a></font></td><td><br>Detection of any edge on RF input</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SSC_START_0"></a><b>SSC_START_0</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_START_0">AT91C_SSC_START_0</a></font></td><td><br>Compare 0</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">23..16</td><td align="CENTER"><a name="SSC_STTDLY"></a><b>SSC_STTDLY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_STTDLY">AT91C_SSC_STTDLY</a></font></td><td><b>Receive/Transmit Start Delay</b><br>If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception/transmission.<br>When the Receiver/Transmitter is programmed to start synchronously with the Transmitter/Receiver, the delay is also applied.<br>Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive/Transmit Sync Data) reception.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..24</td><td align="CENTER"><a name="SSC_PERIOD"></a><b>SSC_PERIOD</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_PERIOD">AT91C_SSC_PERIOD</a></font></td><td><b>Receive/Transmit Period Divider Selection</b><br>This field selects the divider to apply to the selected Receive/Transmit Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive/Transmit Clock.</td></tr>
</null></table>
<a name="SSC_TFMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_TFMR  <i>Transmit Frame Mode Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TFMR">AT91C_SSC_TFMR</a></i> 0xFFFD401C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">4..0</td><td align="CENTER"><a name="SSC_DATLEN"></a><b>SSC_DATLEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_DATLEN">AT91C_SSC_DATLEN</a></font></td><td><b>Data Length</b><br>The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver/Transmitter. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_DATDEF"></a><b>SSC_DATDEF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_DATDEF">AT91C_SSC_DATDEF</a></font></td><td><b>Data Default Value</b><br>This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_MSBF"></a><b>SSC_MSBF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_MSBF">AT91C_SSC_MSBF</a></font></td><td><b>Most Significant Bit First</b><br>0: The lowest significant bit of the data register is sampled first in the bit stream.<br>1: The most significant bit of the data register is sampled first in the bit stream.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..8</td><td align="CENTER"><a name="SSC_DATNB"></a><b>SSC_DATNB</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_DATNB">AT91C_SSC_DATNB</a></font></td><td><b>Data Number per Frame</b><br>This field defines the number of data words to be received/transfered after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19..16</td><td align="CENTER"><a name="SSC_FSLEN"></a><b>SSC_FSLEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSLEN">AT91C_SSC_FSLEN</a></font></td><td><b>Receive/Transmit Frame Sync length</b><br>Receive:<br>This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. If 0, the Receive Frame Sync Sig-nal is generated during one Receive Clock period and up to a 16-clock period pulse length is possible.<br>Transmit:<br>This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..20</td><td align="CENTER"><a name="SSC_FSOS"></a><b>SSC_FSOS</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS">AT91C_SSC_FSOS</a></font></td><td><b>Receive/Transmit Frame Sync Output Selection</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SSC_FSOS_NONE"></a><b>SSC_FSOS_NONE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_NONE">AT91C_SSC_FSOS_NONE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SSC_FSOS_NEGATIVE"></a><b>SSC_FSOS_NEGATIVE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_NEGATIVE">AT91C_SSC_FSOS_NEGATIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Negative Pulse</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SSC_FSOS_POSITIVE"></a><b>SSC_FSOS_POSITIVE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_POSITIVE">AT91C_SSC_FSOS_POSITIVE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Positive Pulse</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SSC_FSOS_LOW"></a><b>SSC_FSOS_LOW</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_LOW">AT91C_SSC_FSOS_LOW</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SSC_FSOS_HIGH"></a><b>SSC_FSOS_HIGH</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_HIGH">AT91C_SSC_FSOS_HIGH</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SSC_FSOS_TOGGLE"></a><b>SSC_FSOS_TOGGLE</b><font size="-1"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSOS_TOGGLE">AT91C_SSC_FSOS_TOGGLE</a></font></td><td><br>Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">23</td><td align="CENTER"><a name="SSC_FSDEN"></a><b>SSC_FSDEN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSDEN">AT91C_SSC_FSDEN</a></font></td><td><b>Frame Sync Data Enable</b><br>0: The TD line is driven with the default value during the Transmit Frame Sync signal.<br>1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24</td><td align="CENTER"><a name="SSC_FSEDGE"></a><b>SSC_FSEDGE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_FSEDGE">AT91C_SSC_FSEDGE</a></font></td><td><b>Frame Sync Edge Detection</b><br>Determines which edge on Frame Sync will generate the interrupt RXSYN/TXSYN in the SSC Status Register.<br>0: Positive Edge Detection<br>1: Negative Edge Detection</td></tr>
</null></table>
<a name="SSC_RHR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_RHR  <i>Receive Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RHR">AT91C_SSC_RHR</a></i> 0xFFFD4020</font></null></ul><br>Right aligned regardless of the number of data bits defined by DATLEN in SSC_RMR<a name="SSC_THR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_THR  <i>Transmit Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_THR">AT91C_SSC_THR</a></i> 0xFFFD4024</font></null></ul><br>Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR<a name="SSC_RSHR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_RSHR  <i>Receive Sync Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_RSHR">AT91C_SSC_RSHR</a></i> 0xFFFD4030</font></null></ul><br>Receive Synchronization Data<a name="SSC_TSHR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_TSHR  <i>Transmit Sync Holding Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_TSHR">AT91C_SSC_TSHR</a></i> 0xFFFD4034</font></null></ul><br>Transmit Synchronization Data<a name="SSC_SR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_SR  <i>Status Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_SR">AT91C_SSC_SR</a></i> 0xFFFD4040</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="SSC_TXENA"></a><b>SSC_TXENA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXENA">AT91C_SSC_TXENA</a></font></td><td><b>Transmit Enable</b><br>0: Transmit is disabled.<br>1: Transmit is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="SSC_RXENA"></a><b>SSC_RXENA</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXENA">AT91C_SSC_RXENA</a></font></td><td><b>Receive Enable</b><br>0: Receive is disabled.<br>1: Receive is enabled.</td></tr>
</null></table>
<a name="SSC_IER"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_IER">AT91C_SSC_IER</a></i> 0xFFFD4044</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="SSC_IDR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_IDR">AT91C_SSC_IDR</a></i> 0xFFFD4048</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="SSC_IMR"></a><h4><a href="#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91_REG">AT91_REG</a></i> SSC_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="AT91SAM7S256_h.html#AT91C_SSC_IMR">AT91C_SSC_IMR</a></i> 0xFFFD404C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SSC_TXRDY"></a><b>SSC_TXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXRDY">AT91C_SSC_TXRDY</a></font></td><td><b>Transmit Ready</b><br>0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR).<br>1: SSC_THR is empty.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="SSC_TXEMPTY"></a><b>SSC_TXEMPTY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXEMPTY">AT91C_SSC_TXEMPTY</a></font></td><td><b>Transmit Empty</b><br>0: Data remains in SSC_THR or is currently transmitted from TSR.<br>1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="SSC_ENDTX"></a><b>SSC_ENDTX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDTX">AT91C_SSC_ENDTX</a></font></td><td><b>End Of Transmission</b><br>0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR.<br>1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="SSC_TXBUFE"></a><b>SSC_TXBUFE</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXBUFE">AT91C_SSC_TXBUFE</a></font></td><td><b>Transmit Buffer Empty</b><br>0: SSC_TCR or SSC_TNCR have a value other than 0.<br>1: Both SSC_TCR and SSC_TNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="SSC_RXRDY"></a><b>SSC_RXRDY</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXRDY">AT91C_SSC_RXRDY</a></font></td><td><b>Receive Ready</b><br>0: SSC_RHR is empty.<br>1: Data has been received and loaded in SSC_RHR.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="SSC_OVRUN"></a><b>SSC_OVRUN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_OVRUN">AT91C_SSC_OVRUN</a></font></td><td><b>Receive Overrun</b><br>0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register.<br>1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="SSC_ENDRX"></a><b>SSC_ENDRX</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_ENDRX">AT91C_SSC_ENDRX</a></font></td><td><b>End of Reception</b><br>0: Data is written on the Receive Counter Register or Receive Next Counter Register.<br>1: End of PDC transfer when Receive Counter Register has arrived at zero.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="SSC_RXBUFF"></a><b>SSC_RXBUFF</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXBUFF">AT91C_SSC_RXBUFF</a></font></td><td><b>Receive Buffer Full</b><br>0: SSC_RCR or SSC_RNCR have a value other than 0.<br>1: Both SSC_RCR and SSC_RNCR have a value of 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="SSC_TXSYN"></a><b>SSC_TXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_TXSYN">AT91C_SSC_TXSYN</a></font></td><td><b>Transmit Sync</b><br>0: A Tx Sync has not occurred since the last read of the Status Register.<br>1: A Tx Sync has occurred since the last read of the Status Register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="SSC_RXSYN"></a><b>SSC_RXSYN</b><font size="-2"><br><a href="AT91SAM7S256_h.html#AT91C_SSC_RXSYN">AT91C_SSC_RXSYN</a></font></td><td><b>Receive Sync</b><br>0: A Rx Sync has not occurred since the last read of the Status Register.<br>1: A Rx Sync has occurred since the last read of the Status Register.</td></tr>
</null></table>
<a name="SSC"></a><h4><a href="AT91SAM7S256_SSC.html#SSC">SSC</a>: <i><a href="AT91SAM7S256_h.html#AT91S_PDC">AT91S_PDC</a></i> SSC  <i>PDC interface</i></h4><ul><null><font size="-2"><li><b>SSC</b> <i><a href="#AT91C_SSC_SSC">AT91C_SSC_SSC</a></i> 0xFFFD4100</font></null></ul></null><hr></html>
